1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically to a semiconductor memory device having a pair of data lines for outputting a content of a memory cell in the form of a differential signal.
2. Description of Related Art
Referring to FIG. 1, there is shown a circuit diagram, corresponding to one bit, of one example of a conventional semiconductor memory device, in which a bipolar differential amplifier circuit is connected to a static memory cell. In the shown example, a pair of complementary digit lines D and DB are pulled up through resistors R1 and R2 to a high voltage supply voltage Vcc, and a memory cell MC is connected between the pair of digit lines D and DB and also connected to a word line WL, so that when the memory cell MC is selected by the word line WL, a content of the memory cell MC is outputted to the pair of digit lines D and DB in the form of a differential voltage signal.
The pair of digit lines D and DB are also connected to a sense amplifier 10, which amplifies the output of the memory cell MC read out on the pair of digit lines D and DB, and supplies the amplified output to a multiplexor and current-to-voltage conversion amplifier circuit 12.
The sense amplifier 10 includes a pair of NPN bipolar transistors Q11 and Q12 having their base connected to the pair of digit lines D and DB, respectively. A collector of each of the bipolar transistors Q11 and Q12 is connected to a high voltage supply voltage Vcc. Emitter of the bipolar transistors Q11 and Q12 are connected to a pair of complementary data lines W and WB, respectively. The pair of data lines W and WB are connected to a drain of a pair of source-grounded N-channel MOS transistors M11 and M12, respectively, which have a gate connected to receive a sense amplifier selection signal YS, so that each of the N-channel MOS transistors M11 and M12 constitutes a constant current source for the bipolar transistors Q11 and Q12. Therefore, the bipolar transistors Q11 and the N-channel MOS transistor M11 constitute an emitter follower circuit, and the bipolar transistor Q12 and the N-channel MOS transistor M12 constitute another emitter follower circuit.
In addition, the pair of dale lines W and WB are respectively connected to a base of a pair of NPN bipolar transistors Q13 and Q14, which have their emitter connected in common to a drain of source-grounded N-channel MOS transistor M13. A gate of the MOS transistor M13 is connected to receive the selection signal YS, so that the N-channel MOS transistor M13 constitutes a constant current source. A collector of each of the pair of NPN bipolar transistors Q13 and Q14 is connected to the multiplexor and amplifier circuit 12. Therefore, the NPN bipolar transistors Q13 and Q14 constitute a differential amplifier, so that an output signal is outputted, in the form of a differential current, from the collector of the NPN bipolar transistors Q13 and Q14. The output signal is selected and level-adjusted in the multiplexor and current-to-voltage conversion amplifier circuit 12, so that a read-out data signal DOUT is outputted from the multiplexor and amplifier circuit 12.
Now, operation of the above mentioned semiconductor memory device will be explained.
A voltage amplitude of a signal read out from the memory cell MC onto the digit lines D and DB, which are at an operation voltage near to the high voltage supply voltage Vcc, is extremely small such as a few ten millivolts to a few hundred millivolts. The sense amplifier 10 receiving the extremely small voltage, converts the extremely small voltage to a low voltage on the order of about 0.8 V, by action of a level shifting emitter follower circuit including the N-channel MOS transistors M11 and M12. The low voltage appears on the pair of data lines W and WB, and is inputted to the differential amplifier composed of the bipolar transistors Q13 and Q14.
However, a voltage difference between the pair of data lines W and WB is extremely small similarly to the voltage difference between the pair of digit lines D and DB. Therefore, an effective circuit can be obtained by constituting the differential amplifier by high sensitive bipolar transistors. On the other hand, the emitter follower circuits including the N-channel MOS transistors are inserted for obtaining the input voltage suitable to the differential amplifier and for electrically separating a signal line load of the differential amplifier circuit from the digit line.
The output of the differential amplifier is supplied from the collector of the bipolar transistors Q13 and Q14, in the form of a differential current, to the multiplexor and amplifier circuit 12. In the multiplexor and amplifier circuit 12, there are provided a plurality of amplifying circuits, and a constant current flows in only a selected one of the plurality of amplifying circuits, for the purpose of selecting one signal from the input signals and transferring the selected input signal. 0f course, a current source for the differential output current is given by the constant current source circuit composed of the N-channel MOS transistor M13 for the differential amplifier. However, when the sense amplifier is not selected, the constant current source circuits for the emitter followers are turned off, and therefore, a consumed electric current is reduced. Otherwise, a current would flow through the emitter follower circuits of all of a large number of differential amplifier circuits, so that a consumed electric power of an overall semiconductor device would inevitably increase.
In the above mentioned conventional semiconductor memory device, when the sense amplifier circuit 10 is selected by the selection signal YS, the constant current begins to flow through the emitter follower circuits. Accordingly, after respective potentials of the data lines W and WB of the emitter follower circuits, which are the input signals supplied to the differential amplifier, have been fixed or settled, the differential amplifier begins to operate.
On the other hand, in a non-selected emitter follower circuits in which the constant current does not flow, the bipolar transistors Q11 and Q12 are in an off condition, and therefore, the potentials of the data lines W and WB are not fixed. This means that the last read-out potential information remains on the the data lines W and WB, or the data lines W and WB assume an indefinite potential due to noises and other factors. Namely, this means that the potentials of the data lines W and WB are in a floating condition. In this condition, if the sense amplifier is selected, a delay occurs until a normal or proper read-out potential information is fixed or settled on the data lines W and WB.
A recent increased memory integration density results in an increased load capacitance of the signal lines of the emitter follower circuit, and therefore, a potential fixing or settling time increases. This is a large hindrance in realizing a high speed operation.